Memory map

section name (description)address spacetotal sizebus widthuser permissions
BIOS0x0000_0000-0x0000_3fff16kb32bit--x
eRAM (on cartridge)0x0200_0000-0x0203_ffff256kb16bitrwx
RAM (cpu embedded)0x0300_0000-0x0300_7fff32kb32 bitrwx
IO (memory-mapped registers)0x0400_0000-0x0400_03ff1kb16 bitrw-
Palette (2 palettes x 256 entries x 15 bit colors)0x0500_0000-0x0500_03ff1kb16 bitrw-
VRAM0x0600_0000-0x0601_7fff96kb16 bitr--
Object Attribute Memory0x0700_0000-0x0700_03ff1kb32 bitrw-
ROM (bios probably points execution to here)0x0800_0000-0x0dff_ffff32mb16 bitr-x
Persistent RAM (basically save files)0x0e00_0000-0x0e00_ffff (can theorhetically be bigger, but is unnecessary)>= 64kb8 bitrw-

Address Bus Width and CPU Read/Write Access Widths Shows the Bus-Width, supported read and write widths, and the clock cycles for 8/16/32bit accesses. Region Bus Read Write Cycles BIOS ROM 32 8/16/32 - 1/1/1 Work RAM 32K 32 8/16/32 8/16/32 1/1/1 I/O 32 8/16/32 8/16/32 1/1/1 OAM 32 8/16/32 16/32 1/1/1 _ Work RAM 256K 16 8/16/32 8/16/32 3/3/6 ** Palette RAM 16 8/16/32 16/32 1/1/2 _ VRAM 16 8/16/32 16/32 1/1/2 * GamePak ROM 16 8/16/32 - 5/5/8 /* GamePak Flash 16 8/16/32 16/32 5/5/8 /* GamePak SRAM 8 8 8 5 ** Timing Notes:

  • Plus 1 cycle if GBA accesses video memory at the same time. ** Default waitstate settings, see System Control chapter. *** Separate timings for sequential, and non-sequential accesses. One cycle equals approx. 59.59ns (ie. 16.78MHz clock). All memory (except GamePak SRAM) can be accessed by 16bit and 32bit DMA.